Memory modules like double data rate (DDR) synchronous dynamic random access memory (SDRAM) are a class of memory capable of providing approximately twice the bandwidth of single data rate SDRAM. DDR SDRAM achieves this increased bandwidth without requiring an increased clock frequency by transferring data on both rising and falling edges of a clock signal. Therefore, the DDR SDRAM is often used in the design of integrated circuits.
A typical DDR memory subsystem includes a memory controller, a physical interface (sometimes referred to as PHY) and the memory modules, for example, DDR memory modules. The memory controller is coupled to the PHY and the PHY is coupled to the memory modules. The memory controller includes an arbiter and a protocol engine. The memory controller receives requests from various system elements of a computing system like processors and input-output (IO) devices. The memory controller processes the received request through an arbitration mechanism, using the arbiter. The protocol engine of the memory controller performs address translation, command scheduling and converts the requests into a sequence of DRAM commands. Then, the address and command along with the data are sent to the PHY.
The PHY receives the data from the memory controller at single data rate (SDR) and converts the data into double data rate (DDR), generates a data strobe (DQS), data queue (DQ) and sends the data to the DDR memory module along with the address and command data.
During a read operation from the memory modules, the PHY receives data at double data rate along with a DQS signal. The PHY converts the received data into single data rate and sends the data to the memory controller.
The PHY also contains delay lines and state machines to control and align skew between the data, strobe signals and the address/command lines using different training routines. The times at which the read data is latched are preferably synchronized relative to the DQS signal so as to latch the read data in the middle of valid data window. A gate signal is used to enable the DQS signal so that correct DQS edges are used. In general, determining the delay to be used in issuing the gate signal is known as gate training.
Existing techniques for gate training may not efficiently determine the delay to be used.